This invention relates to faults in integrated circuits, and more specifically to a method for locating faults in programmable logic devices.
An important tool for semiconductor yield enhancement is fault localization. Conventional techniques of fault localization are applicable mainly to memory elements because they rely on a direct correspondence of memory address to a specific cell. It should be noted that using memory elements for failure analysis purpose is not limited to stand alone memory devices because many microprocessor or ASIC logic parts have some kind of on chip embedded or cache memory.
The memory cells in most semiconductor devices are built using two to three levels of metal. On the other hand, modern process technologies have more than eight layers of metals. Thus, memory yields are relatively insensitive to defects in higher level metals, thus cannot be relied on for yield enhancement for those levels.
One type of memory rich devices that use many levels of metal is field programmable gate arrays (FPGAs). A FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by programmable line segments (such as single length, intermediate length and long interconnect lines) that are controlled by a plurality of programmable interconnection points (PIPs). The CLBs, IOBs, and the PIPs are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and PIPs are configured. The configuration data is typically organized into frames. The configuration bitstream may be read from an external memory (e.g., an external PROM). The collective states of the individual memory cells then determine the function of the FPGA. In addition to configuration memory, many FPGAs also have embedded memories (e.g., LUT RAMs and BLOCK RAMs).
In FPGA, the interconnect resources use all layers of metal. Unlike memories where fault localization is a matter of translating the faulty logical address to its corresponding physical location, interconnect faults do not have such direct correspondence. Thus, it is important to develop a new fault localization technique that can locate faults in multiple metal layers.
The present invention involves a method for locating faults in a programmable logic device. The programmable logic device contains a plurality of nets, and each net contains a plurality of line segments connected by PIPs. A faulty net (among the plurality of nets) is first identified using conventional methods. In order to locate a fault in a net, a new design is constructed by replacing one of the plurality of line segments or PIPs with an alternative line segment/PIP. The new design is tested to determine if the fault has been removed as a result of the replacement. If the fault is not removed, the previous line segment/PIP is restored, and another line segment/PIP is replaced. This process is repeated until a design without fault is found. The location of the fault should correspond to this line segment/PIP.
This method can be used to locate both open and short faults. In one embodiment of locating short faults, the line segments of two suspected nets may be shorted to each other. The above mentioned new designs are constructed and tested for each net. This allows the faulty line segment of each net to be individually located.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.